The present invention relates to a semiconductor memory device composed of double gate type field effect transistors having control gates and floating gates for accumulating charges. Moreover, it relates to a semiconductor memory device which assures high charge injection efficiency and also high read-out efficiency.
Some nonvolatile semiconductor memory devices use double gate type field effect transistors as the memory elements. FIG. 1 shows a sectional view of the conventional double gate type field effect transistor. The structure and principle or operation of a transistor of this type are disclosed in U.S. Pat. No. 3,984,822.
The transistor shown in FIG. 1 includes, on a silicon semiconductor substrate 10 of the one conductivity type (P type), a source region 11 of the opposite conductivity type (N type), a drain region 12, an electrically floating gate 13, and a control gate 15. The reference numeral 14 is an insulating layer (silicon oxide), while 16 represents lead-out electrodes connected to the source 11 and drain 12. Reference number 17 is a high concentration region of the first conductivity type (P type).
The operation of this transistor as a memory element is explained hereunder.
(a) Injection of charge into the floating gate as the write operation:
First, the substrate 10 and source region 11 are set to the same potential (ground potential), and a positive voltage of about 15 V, for example, is applied to the drain region 12 while a positive voltage of about 20 V (write voltage), for example, is applied to the control gate 15. In this condition, the transistor is fully saturated, and the channel between the source region 11 and drain region 12 is in the pinch-off condition and the carriers of the channel are sufficiently accelerated by the high electrical field in the depletion layer between the pinch-off point and the drain region 12 to cause impact ionization. As a result, the avalanche phenomenon of electrons occurs. In this condition, a many carriers (hot carriers) having a high energy exists in the depletion layer between the pinch-off point and the drain region 12. The hot electrons having an energy higher in amount than the energy barrier between the substrate 10 and insulating layer 14 move in the insulating layer 14 due to the field between the control gate 15 and substrate 10 and then are injected into the floating gate 13.
In case the substrate 10 is N type and both source region 11 and drain region 12 are P type, the direction of the field is inverted from the abovementioned operation and holes are injected into the floating gate 13. Once the charge is injected into the floating gate 13, such charge is accumulated semi-permanently in the floating gate 13. The difference of conductivity of the channel of the transistor due to the existence of the accumulated charge is used as the stored information.
(b) Read-out operation:
When electrons are accumulated in the floating gate 13, the threshold voltage becomes high. Therefore, an intermediate voltage (read-out voltage) between the threshold voltage when no electrons are accumulated and that when electrons are accumulated is applied to the control gate 15. The transistor has a low conductivity or is not conductive when electrons are accumulated in the floating gate 13, or has a high conductivity when electrons are not accumulated.
(c) Erasure or removal of charges:
Charges can be removed by irrading the transistor with ultra-violet rays and other electromagnetic waves or radioactive rays.
In the prior art in order to more efficiently execute the write operation explained above, the high concentration region 17 (of the same conductivity type (P type) as the substrate 10) is formed on the substrate 10 between the source region 11 and drain region 12. Formation of this high concentration region 17 narrow the depletion layer existing in the channel near the drain region at the time of the write operation. Therefore, the electrical field in the depletion layer is intensified and as a result the energy of carriers accelerated in the depletion layer becomes high, also increasing the probability of hot carrier generation. As a result, the efficiency of injecting hot carriers into the floating gate 13 is improved. This lowers the write voltage.
However, the read-out operation efficiency is degraded when the high concentration region 17 is provided. Namely, since the channel concentration becomes heavy, the threshold voltage becomes high and the conductance gm of a transistor becomes small. Thus, a high power supply voltage is required in order to increase the read-out voltage to be applied to the control gate 15. Moreover, in the event that the read-out voltage is lowered, the difference between the threshold voltage when no electrons are injected to the floating gate 13 and the read-out voltage becomes small, slowing the read-out operation. On the other hand, it is conceivable to widen the channel of the transistor in order to increase the conductance gm, but this would also increase the area occupied by the transistor and tend to reduce the integration density. Obtaining the high concentration channel is equivalent to the setting of inconvenient conditions for a highly efficient read-out operation.